Systems performance, such as for a system-on-chip (SOC), benefits from increased memory bandwidth. Such bandwidth must be supported internally on the SOC as well as between the SOC and the memory chips. On-chip data pathways are limited in bandwidth because, for example, propagation times and on-chip variation prevent timing closure at high frequency when the data pathway must span a long distance synchronously, and increasing the width of the data pathway degrades its efficiency for normal-sized data units. For these reasons there is a trend to use multiple parallel data pathways, each running at moderate frequency and with a moderate bus width. All such pathways are functionally identical; they run from the same source to the same destination and data can travel on any one of them without restriction, save for differences in performance.
If one pathway's bandwidth is under-utilized then part of the system bandwidth is wasted. This problem may be relatively easy to solve for a single data source that knows its own traffic requirements, but it is prohibitively expensive to provide all the sources in the system access to all the routes. Also it may be impossible for some sources to route data arbitrarily because of ordering restrictions or it may be undesirable because it makes quality-of-service guarantees more difficult to achieve. Therefore, many of the sources in a system may be restricted to using a subset of the routes or only one fixed route.